#Slice it forward code

Dependence-based scheduling revisited: A tale of two baselines. In Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA), pages 206-218, June 1997. Complexity-effective superscalar processors. In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 694-701, 2011. Cacti-p: Architecture-level modeling for sram-based structures with advanced leakage reduction techniques. t al.(2011)Li, Chen, Ahn, Brockman, and Jouppi]1057_cactiS.In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 469-480, Dec. McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. In Proceedings of the 25th International Symposium on High-Performance Computer Architecture (HPCA), pages 558-569, 2019. Freeway: Maximizing mlp for slice-out-of-order execution. In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA), pages 71-81, 2002. An instruction set and microarchitecture for instruction level distributed processing. In Proceedings of the 26th IEEE International Symposium on High Performance Computer Architecture (HPCA), pages 383-396, 2020. CASINO core microarchitecture: Generating out-of-order schedules using cascaded in-order scheduling windows. Synthesis Lectures on Computer Architecture. Computer Architecture Performance Evaluation Methods. In Proceedings of the 38th Annual International Symposium on Computer Architecture (ISCA), pages 117-128, 2011. OUTRIDER: Efficient memory latency tolerance with decoupled strands. In Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), pages 272-284, 2015.

#Slice it forward code

ACM Transactions on Architecture and Code Optimization (TACO), 11 (3): 28, 2014.

An evaluation of high-level mechanistic core models. In Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 319-330, 2005. 'flea-flicker' multipass pipelining: an alternative to the high-power out-of-order offense. In Proceedings of the 26th IEEE International Symposium on High Performance Computer Architecture (HPCA), pages 424-434, 2020. Delay and bypass: Ready and criticality aware instruction scheduling in out-of-order processors. FSC improves performance by 9.7% on average compared to Freeway, the state-of-the-art sOoO core, across the SPEC CPU2017 benchmarks, while incurring reduced hardware complexity and a similar power budget. Finally, FSC eliminates the need for dynamic memory disambiguation by replicating store-address instructions across queues. Moreover, FSC puts load-consumers that depend on L1 D-cache misses on the side to enable younger independent load-consumers to execute faster. FSC does so by identifying and steering forward slices (rather than backward slices) to dedicated in-order FIFO queues. In this paper, we propose Forward Slice Core (FSC), a novel core microarchitecture that builds on a stall-on-use in-order core and extracts more instruction-level and memory-hierarchy parallelism than slice-out-of-order cores. Unfortunately, constructing backward slices is imprecise and hardware-inefficient, leaving performance on the table. Recently proposed slice-out-of-order (sOoO) cores identify backward slices of memory operations which they execute out-of-order with respect to the rest of the dynamic instruction stream for increased instruction-level and memory-hierarchy parallelism. A processor architecture should ideally provide high performance in a power- and cost-efficient manner. In-order cores, in contrast, are less complex and have a smaller power budget, but offer low performance. Superscalar out-of-order cores deliver high performance at the cost of increased complexity and power budget.